In modern electronic measuring devices such as spectrum analyzers or network analyzers, the analog measurement data are sampled and digitized with a high-speed analog/digital converter and are stored in a memory for later processing. It is important that the reading of the data into the memory occur continuously and uninterrupted within the measuring time that is predetermined by the measuring device, since data gaps can falsify the measuring result and render it unusable for a further processing. Therefore, static memories (RAM, or respectively, SRAM) have been used exclusively for the storage in measuring devices of this type. However, the storage size of such static memories is limited for technological reasons, thus necessitating the use of many storage modules for receiving large data volumes during long measuring times.
Modern synchronous dynamic memories (DRAM, or respectively, SDRAM) such as are used in digital computers do have a large storage capacity , but they cannot be used for continuous uninterrupted data recording during a long measuring time, since they periodically require what are known as preparatory (or priming) phases at definite time intervals, of 4 or 8 measuring values, for example, by which phases a continuous reading , of a large data volume is interrupted. Further, despite their high recording speed, on average, such dynamic memories have a relatively low recording speed as a consequence of the required preparatory times. In addition, such dynamic memories require refreshing processes at defined time intervals so that the memory contents are not falsified. For this reason, such dynamic memories have until now usually been used only in digital computers, where short-term delays due to refreshing, or respectively, preparatory times do not play a role.
With additional storage modules (FIFO) which intermediately store the continuous data stream for the length of a read-in phase, for example, such dynamic memories could be expanded even for continuous and uninterrupted read-in of a large data volume; however, this requires a relatively large and expensive hardware outlay, and the achievable average read-in speed becomes even lower.
In dynamic memories of this type, it is known per se to execute refreshing processes in one part of the memory at the same time as storage cycles are being executed in another part of the memory. See German patent document DE-AS 22 47 835, or respectively, German patent 26 37 004.
There is also known an arrangement from East German patent document DD 28174 in which the storage elements can respectively record only a single data word before a new preparation is already required. Furthermore, with this known arrangement, only data word sequences that can be divided by two can be read in without data loss, since all the data words with even addresses are read into one storage element, and all the data words with odd addresses are read into the other storage element, respectively.
An object of the invention is to provide an arrangement that, with the lowest possible wiring outlay, an arbitrarily large data volume can be read into a memory continuously and uninterrupted during an arbitrarily long measuring time, without data being lost.
To that end, in an embodiment, the invention provides a circuit for the continuous and uninterrupted read-in of a given volume of data from an electronic measuring device, into a memory, comprising:
at least two dynamic storage elements having an active phase and an inactive phase; and
a controller operatively connected and configured to control said dynamic storage elements, the controller configured to direct said data to a dynamic storage element prepared for its active phase while another storage element is in its inactive preparatory phase.
In an embodiment, the invention also provides that the controller is configured to control refreshing of the storage elements such that the data in the storage elements are refreshed only after completion of the read-in of all of the entire volume of data from the electronic measuring devices.
In the inventive arrangement, several consecutive data words are read in each storage element, respectively, such as 8, 256, 512 or 1024 data words in succession, for example, which are respectively preceded by a single preparatory time of only six data words, for example. It is thus possible to read in arbitrarily long odd data word sequences, which is particularly advantageous if the read-in of the data from a data generator is to occur into a ring memory. periodically and synchronously and so an odd data sequence length is selected. In the inventive arrangement, the data word sequence which is respectively read into a storage element during the active phase could also be shortened by one or more data words without resulting in data loss.
An inventive arrangement can be constructed quite economically with conventional DRAMs; thus, an expensive FIFO memory becomes superfluous. In addition, the high read-in speed of such DRAMs can be fully exploited, and a high read-in speed of the overall arrangement is thus achieved.
These and other features of the invention are discussed in greater detail below in the following detailed description of the presently preferred embodiments with reference to the accompanying drawings: